The invention is directed to a circuit arrangement for adding or subtracting operands coded in BCD-code or binary-code upon employment of a binary adder.
Up to now, different circuit arrangements have been proposed for adding or subtracting operands coded in binary code or BCD code. Given additions or subtractions of operands in the binary code, a circuit for generating a one's or a two's complement was thereby necessary. Given BCD operands, by contrast, a circuit for generating the nine's complement was required.
Binary adders are known (see, for example, U. Tietze, Ch. Schenk, Halbleiterschaltungstechnik, 4th Edition, Springer Verlag, Berlin Heidelberg New York, 1978, pages 475, 476). It is also known to add or subtract BCD numbers upon employment of binary adders. Two binary adders, however, are required for this purpose. (See op. cit., page 477). The second binary adder is required in order to correct the result of the first binary adder. This is necessary when a carry occurs in a decade. A 6 must then be added to the result of the first binary adder. This BCD number, however, can contain a pseudo-tetrade. In this case, the number 6 must still be added in order to eliminate the pseudo-tetrade. The correction of the result of the first binary adder ensues with the assistance of the second binary adder. The overall outlay for the circuit arrangement for adding PCD numbers is thus relatively great and the circuit works relatively slowly.